Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020.

Apple Announces The Apple Silicon M1: Ditching x86 - What to Expect, Based on A14.

TSMC Boosts CapEx by $1 Billion, Expects N5 Node to Be Major Success.

‘Better Yield on 5nm than 7nm’: TSMC Update on Defect Rates for N5.

Alongside the new 112G SerDes, the company says it is set to enable a complete suite of PHYs, switches, DPUs, custom processors, controllers, and accelerators built on 5nm, and that this initial offering is but the first step. Marvell says it is already engaged with its custom ASIC customers across multiple markets with the 112G implementation. Regular readers may identify that NVIDIA’s RTX 3090 uses PAM4 signaling (on N7) to enable over 1000 GB/s of bandwidth with Micron’s GDDR6X – it can also be run in NRZ mode for lower power if needed. As we move to even faster speeds, PAM4 will become a necessity to enable them. PAM4 has been enabled at lower SerDes speeds and at 112G before, but not for TSMC N5. This enables double the bandwidth, but does require some extra circuitry. a 1-bit operation which can be a 0 or a 1, known as NRZ (non-return to zero) - however Marvell’s solution enables 2-bit operation, such as a 00, 01, 10, or 11, known as PAM4 (Pulse Amplitude Modulation). We typically expect data to travel down a connection like this as a series of ones and zeros, i.e. Marvell is claiming that its new solution enables a significant power reduction in energy per bit transferred – up to 25% compared to equivalent TSMC 7nm offerings, along with tight power/thermal constraints and a >40dB insertion loss. These sorts of connections have a number of measurements to compare them to other 112G solutions: the goal is to not only meet the standard, but offer a solution that uses less power, but also a lower potential error rate, especially for high-speed high-reliability infrastructure applications. Several companies have 112G IP available, however Marvell is the first to enable it in 5nm, ensure it is hardware validated, and offer it for licensing. Current high-speed connections rely on 56G connections, and so moving up to 112G enables double the speed.

Modern chip-to-chip networking infrastructure relies on high speed SerDes connections to enable a variety of different protocols at a range of speeds, typically in Ethernet, fiber optics, storage, and connectivity fabrics.

Today Marvell is announcing its DSP-based 112G SerDes solution for licensing. We can now add another to that list, but it’s not a standard SoC: here we have IP for a SerDes connection, now validated and ready for licensing in TSMC N5. So far we have three products in the market built on TSMC’s N5 process: the Huawei Kirin 9000 5G SoC, found in the Mate 40 Pro, the Apple A14 SoC, found in the iPhone 12 family, and the Apple M1 SoC, which is in the new MBA/MBP and Mac Mini.

56g vs 112g serdes